TEST_NAME         = u2a_incr_payld_bd_parity
SVSEED            = random
TB_FILENAME       = ${SOC_HOME}/uart_ctrl/tb/sv/uart_ctrl_top.sv
VERBOSITY         = MEDIUM
WORKSHOP_MODE     = NONE


OPTIONS    = +incdir+${SOC_HOME}/interface_uvc_lib/apb/sv \
             +incdir+${SOC_HOME}/interface_uvc_lib/uart/sv \
             +incdir+${SOC_HOME}/uart_ctrl/sv  \
             +incdir+${SOC_HOME}/uart_ctrl/sv/sequence_lib  \
             +incdir+${SOC_HOME}/uart_ctrl/tb/sv  \
             +incdir+${SOC_HOME}/uart_ctrl/tb/tests  \
             -timescale=1ns/1ns \
             ${SOC_HOME}/interface_uvc_lib/apb/sv/apb_pkg.sv \
             ${SOC_HOME}/interface_uvc_lib/uart/sv/uart_pkg.sv \
             ${SOCV_KIT_HOME}/designs/socv/rtl/rtl_lpw/opencores/uart16550/rtl/uart_defines.v \
             -F ./flist \
             ${SOC_HOME}/uart_ctrl/sv/uart_ctrl_defines.svh \
             ${SOC_HOME}/uart_ctrl/sv/uart_ctrl_pkg.sv \
             -l vcs_$(TEST_NAME).log \
             +define+UART_ABV_ON \
             +define+LITLE_ENDIAN \
             +define+DYNAMIC_SIM \
             $(TB_FILENAME) 

VCS = vcs -ntb_opts uvm-1.1 -sverilog +define+$(WORKSHOP_MODE)

#******************************************************************************#
# Targets
#******************************************************************************#

test: comp sim 

comp:
	${VCS} $(OPTIONS)
sim:
	simv +UVM_TESTNAME=$(TEST_NAME) -l simv.log +ntb_random_seed=${SVSEED} +UVM_VERBOSITY=$(VERBOSITY)

clean:
	rm -rf INCA* *.log *.key csrc simv simv.daidir simv.vdb vc_hdrs.h 

